Design Rules of Crystalline Silicon 1

In a conventional p-type crystalline silicon (c-Si) wafer based solar cell (see diagram above), the yellow n-doped layer (emitter layer) is much thinner than the rest of the wafer.  This is because most light is absorbed close to the front surface of the solar cell (first 10 microns).  A thin front emitter layer allows the excited charge carriers to be within diffusion lengths of the p-n junction.

There are 3 parts to the charge collection process: the emitter layer, the metal contacts, and the back contact.  Aluminium is used as a cheap conductor for metal contacts, which is more conductive than the emitter layer.  Electrons will have to diffuse laterally through the emitter layer to the metal contacts to be collected.

In order to reduce SRH recombination for higher carrier lifetimes, the surface recombination velocity has to be reduced.  This surface recombination arises due to the many defects on a bare c-Si surface, where surface silicon atoms have valence electrons that cannot make molecular orbitals with absent neighbouring atoms.  These are called dangling bonds.  Since most carriers are generated close to the front surface, high surface recombination velocity will result in large losses of carriers, and thereby resulting in lower J_sc.

There are 2 ways to reduce surface recombination.  Firstly, a thin insulator layer can be deposited on the front surface, which restores the bonding environment of the silicon atoms and force electrons to move inside the emitter layer.  Silicon oxide and silicon nitride are the usual chemical passivation layers used.

Secondly, the minority charge carrier density at the surface region limits the surface recombination velocity, and hence has to be reduced.  This can be done by increasing the p-layer's doping, but this also reduces the diffusion lengths of minority holes in the emitter layer.  Hence, it is not viable for the whole emitter layer.

However, this can be applied at the metal-emitter interface region, where an insulating passivation layer cannot be used.  There is a high interface recombination velocity at the metal-emitter interface.  Moreover, the metal-semiconductor interface induces a barrier for majority charge carriers, which gives rise to higher contact resistance.  Hence, the area of contact between the metal and emitter should be reduced, while the emitter directly under the metal contact should be heavily doped to N+ or N++.



Reference:
4.3 Design Rules of Crystalline Silicon, Delft University of Technology, https://www.youtube.com/watch?v=qmbrGk-c-P8